`timescale 1ns / 1ps
module top_aurora_loop(
	input	wire		clk 		,
//	input 	wire 		rst_n 		,
	output 	wire 		led 		,
//	output 	wire 		tx_dis		,

	input 	wire 		REF_CLK_P 	,
	input 	wire 		REF_CLK_N 	,
	
	output wire        SFP_TX_DIS1,
	output wire        SFP_TX_DIS2,

	input 	wire 		RXP 		,
	input 	wire 		RXN 		,
	output 	wire 		TXP 		,
	output 	wire 		TXN 		
    );


	assign SFP_TX_DIS1 = 1'b0;
	assign SFP_TX_DIS2 = 1'b0;

wire [0 : 31] 	s_axi_tx_tdata		;// 发送数据端口				
wire [0 : 3] 	s_axi_tx_tkeep		;			
wire 			s_axi_tx_tlast		;	
wire 			s_axi_tx_tvalid		;		
wire 			s_axi_tx_tready		;
wire 			s_axi_ufc_tx_tvalid	;// 发送流控端口			
wire [0 : 2] 	s_axi_ufc_tx_tdata	;				
wire 			s_axi_ufc_tx_tready	;			
wire [0 : 31] 	m_axi_rx_tdata		;// 接收数据端口				
wire [0 : 3] 	m_axi_rx_tkeep		;			
wire 			m_axi_rx_tlast		;	
wire 			m_axi_rx_tvalid		;		
wire [0 : 31] 	m_axi_ufc_rx_tdata	;// 接收流控数据端口					
wire [0 : 3] 	m_axi_ufc_rx_tkeep	;				
wire 			m_axi_ufc_rx_tlast	;		
wire 			m_axi_ufc_rx_tvalid	;			

wire 			hard_err			;// 物理层错误
wire 			soft_err			;// 链路层错误
wire 			frame_err			;// 帧错误

wire 			reset				;// 复位信号，正确的复位才能使收发器正常工作
wire 			gt_reset			;

wire 			channel_up			;// 链接信号
wire [0 : 0] 	lane_up				;		
wire 			crc_valid			;
wire 			crc_pass_fail_n		;


// GTP 收发通道
wire [0 : 0] 	txp					;	
wire [0 : 0] 	txn					;	
wire [0 : 0] 	rxp					;
wire [0 : 0] 	rxn					;

wire 			tx_lock					;		
wire 			tx_resetdone_out		;			
wire 			rx_resetdone_out		;			
wire 			link_reset_out			;			
wire 			init_clk_in				;// GTP初始化时钟		
wire 			user_clk_out			;// 系统稳定的时钟			
wire 			pll_not_locked_out		;			
wire 			sys_reset_out			;// 系统复位信号
wire 			gt_refclk1_p			;// GTP 通道参考时钟	
wire 			gt_refclk1_n			;	
wire 			sync_clk_out			;	
wire 			gt_reset_out			;	
wire 			gt_refclk1_out			;	
wire 			gt0_pll0refclklost_out	;			
wire 			quad1_common_lock_out	;			
wire 			gt0_pll0outclk_out		;		
wire 			gt0_pll1outclk_out		;		
wire 			gt0_pll0outrefclk_out	;			
wire 			gt0_pll1outrefclk_out	;			


wire 			sys_rst 				;//用户模块复位信号(高有效)，当前已经链接上，并且系统复位结束
wire 			rst 					;
wire 			error 					;


//assign rst  = ~rst_n;
assign rst  = 1'b0;

assign led = ~error;
//assign tx_dis = 1'b0;
assign {TXP, TXN} = {txp, txn};
assign {rxp, rxn} = {RXP, RXN};
assign {gt_refclk1_p, gt_refclk1_n} = {REF_CLK_P, REF_CLK_N};

assign sys_rst = ~(channel_up & lane_up & (~sys_reset_out));
assign init_clk_in = clk;
assign drpclk_in = clk;

gtp_reset_control  inst_gtp_reset_control (
	.clk             (init_clk_in),
	.rst             (rst),
	.channel_link_up (channel_up),
	.lane_link_up    (lane_up),
	.reset           (reset),
	.gt_reset        (gt_reset)
);

gtp_tx inst_gtp_tx (
	.clk                 (user_clk_out),
	.rst                 (sys_rst),
	.s_axi_tx_tdata      (s_axi_tx_tdata),
	.s_axi_tx_tkeep      (s_axi_tx_tkeep),
	.s_axi_tx_tlast      (s_axi_tx_tlast),
	.s_axi_tx_tvalid     (s_axi_tx_tvalid),
	.s_axi_tx_tready     (s_axi_tx_tready),
	.s_axi_ufc_tx_tvalid (s_axi_ufc_tx_tvalid),
	.s_axi_ufc_tx_tdata  (s_axi_ufc_tx_tdata),
	.s_axi_ufc_tx_tready (s_axi_ufc_tx_tready)
);

gtp_rx  inst_gtp_rx (
	.clk                 (user_clk_out),
	.rst                 (sys_rst),
	.m_axi_rx_tdata      (m_axi_rx_tdata),
	.m_axi_rx_tkeep      (m_axi_rx_tkeep),
	.m_axi_rx_tlast      (m_axi_rx_tlast),
	.m_axi_rx_tvalid     (m_axi_rx_tvalid),
	.m_axi_ufc_rx_tdata  (m_axi_ufc_rx_tdata),
	.m_axi_ufc_rx_tkeep  (m_axi_ufc_rx_tkeep),
	.m_axi_ufc_rx_tlast  (m_axi_ufc_rx_tlast),
	.m_axi_ufc_rx_tvalid (m_axi_ufc_rx_tvalid),
	.error               (error)
);

aurora_8b10b_0 aurora_8b10b_0 (
  	.s_axi_tx_tdata(s_axi_tx_tdata),                  // input wire [0 : 31] s_axi_tx_tdata
  	.s_axi_tx_tkeep(s_axi_tx_tkeep),                  // input wire [0 : 3] s_axi_tx_tkeep
  	.s_axi_tx_tlast(s_axi_tx_tlast),                  // input wire s_axi_tx_tlast
  	.s_axi_tx_tvalid(s_axi_tx_tvalid),                // input wire s_axi_tx_tvalid
  	.s_axi_tx_tready(s_axi_tx_tready),                // output wire s_axi_tx_tready
  	.s_axi_ufc_tx_tvalid(s_axi_ufc_tx_tvalid),        // input wire s_axi_ufc_tx_tvalid
  	.s_axi_ufc_tx_tdata(s_axi_ufc_tx_tdata),          // input wire [0 : 2] s_axi_ufc_tx_tdata
  	.s_axi_ufc_tx_tready(s_axi_ufc_tx_tready),        // output wire s_axi_ufc_tx_tready
  	.m_axi_rx_tdata(m_axi_rx_tdata),                  // output wire [0 : 31] m_axi_rx_tdata
  	.m_axi_rx_tkeep(m_axi_rx_tkeep),                  // output wire [0 : 3] m_axi_rx_tkeep
  	.m_axi_rx_tlast(m_axi_rx_tlast),                  // output wire m_axi_rx_tlast
  	.m_axi_rx_tvalid(m_axi_rx_tvalid),                // output wire m_axi_rx_tvalid
  	.m_axi_ufc_rx_tdata(m_axi_ufc_rx_tdata),          // output wire [0 : 31] m_axi_ufc_rx_tdata
  	.m_axi_ufc_rx_tkeep(m_axi_ufc_rx_tkeep),          // output wire [0 : 3] m_axi_ufc_rx_tkeep
  	.m_axi_ufc_rx_tlast(m_axi_ufc_rx_tlast),          // output wire m_axi_ufc_rx_tlast
  	.m_axi_ufc_rx_tvalid(m_axi_ufc_rx_tvalid),        // output wire m_axi_ufc_rx_tvalid
  	.hard_err(hard_err),                              // output wire hard_err
  	.soft_err(soft_err),                              // output wire soft_err
  	.frame_err(frame_err),                            // output wire frame_err
  	.channel_up(channel_up),                          // output wire channel_up
  	.lane_up(lane_up),                                // output wire [0 : 0] lane_up
  	.txp(txp),                                        // output wire [0 : 0] txp
  	.txn(txn),                                        // output wire [0 : 0] txn
  	.reset(reset),                                    // input wire reset
  	.gt_reset(gt_reset),                              // input wire gt_reset
  	.loopback(3'b000),                                // input wire [2 : 0] loopback
  	.rxp(rxp),                                        // input wire [0 : 0] rxp
  	.rxn(rxn),                                        // input wire [0 : 0] rxn
  	// .crc_valid(crc_valid),                            // output wire crc_valid
  	// .crc_pass_fail_n(crc_pass_fail_n),                // output wire crc_pass_fail_n
  	.drpclk_in(drpclk_in),                            // input wire drpclk_in
  	.drpaddr_in('d0),                          // input wire [8 : 0] drpaddr_in
  	.drpen_in(1'b0),                              	  // input wire drpen_in
  	.drpdi_in('d0),                              // input wire [15 : 0] drpdi_in
  	.drprdy_out(drprdy_out),                          // output wire drprdy_out
  	.drpdo_out(drpdo_out),                            // output wire [15 : 0] drpdo_out
  	.drpwe_in(1'b0), 	                              // input wire drpwe_in
  	.power_down(1'b0 ),                          	  // input wire power_down
  	.tx_lock(tx_lock),                                // output wire tx_lock
  	.tx_resetdone_out(tx_resetdone_out),              // output wire tx_resetdone_out
  	.rx_resetdone_out(rx_resetdone_out),              // output wire rx_resetdone_out
  	.link_reset_out(link_reset_out),                  // output wire link_reset_out
  	.init_clk_in(init_clk_in),                        // input wire init_clk_in
  	.user_clk_out(user_clk_out),                      // output wire user_clk_out
  	.pll_not_locked_out(pll_not_locked_out),          // output wire pll_not_locked_out
  	.sys_reset_out(sys_reset_out),                    // output wire sys_reset_out
  	.gt_refclk1_p(gt_refclk1_p),                      // input wire gt_refclk1_p
  	.gt_refclk1_n(gt_refclk1_n)                      // input wire gt_refclk1_n
  	// .sync_clk_out(sync_clk_out),                      // output wire sync_clk_out
  	// .gt_reset_out(gt_reset_out),                      // output wire gt_reset_out
  	// .gt_refclk1_out(gt_refclk1_out),                  // output wire gt_refclk1_out
  	// .gt0_pll0refclklost_out(gt0_pll0refclklost_out),  // output wire gt0_pll0refclklost_out
  	// .quad1_common_lock_out(quad1_common_lock_out),    // output wire quad1_common_lock_out
  	// .gt0_pll0outclk_out(gt0_pll0outclk_out),          // output wire gt0_pll0outclk_out
  	// .gt0_pll1outclk_out(gt0_pll1outclk_out),          // output wire gt0_pll1outclk_out
  	// .gt0_pll0outrefclk_out(gt0_pll0outrefclk_out),    // output wire gt0_pll0outrefclk_out
  	// .gt0_pll1outrefclk_out(gt0_pll1outrefclk_out)     // output wire gt0_pll1outrefclk_out
);






	ila_STATUS ila_STATUS (
	.clk(user_clk_out), // input wire clk


	.probe0(channel_up), // input wire [0:0]  probe0  
	.probe1(lane_up), // input wire [0:0]  probe1 
	.probe2(hard_err), // input wire [0:0]  probe2 
	.probe3(frame_err) // input wire [0:0]  probe3
);














endmodule